The present invention relates to a semiconductor test circuit such as a built-in self test (hereinafter called “BIST”) circuit or the like used to test the operation of a circuit: such as a semiconductor memory device, and particularly to a semiconductor test circuit having a self monitor mode for performing a self test and a direct access mode for directly testing a circuit.
A BIST circuit built in a large scale integration (hereinafter called LSI) has heretofore been used for testing the operation of a semiconductor memory device or the like as has been described in, for example, Japanese Patent Publication Laid-Open No. 1998-199294. As a method of testing the BIST circuit itself, the following two methods are generally known.
According to the first method, a scan circuit is inserted into a BIST circuit to detect a circuit failure.
According to the second method, signals of a BIST circuit are fetched into external terminals (external pins) of LSI and monitored (detected) by a tester, whereby a circuit failure is detected.
However, the conventional first and second methods respectively involve the following problems.
As to the first method, an actual functional operation of the BIST circuit per se cannot be tested because the BIST circuit is examined through the scan circuit. Therefore, a failure in the actual functional operation of the BJST circuit, and a timing failure in the BIST circuit cannot be examined.
As to the second method, there is a need to fetch a plurality of signals of the BIST circuit to LS external pins through a plurality of wirings respectively. Therefore, a wiring delay for signal transmission exists between the BIST circuit and each LSI external pin. Therefore, timing design at LSI levels of the plurality of signals is needed to assure a high-speed operation for testing, and hence a burden on a designer increases. The present method is accompanied by a problem that LSI external pins corresponding to the number of pins included in the BIST circuit, are required, and a small pin package falls short of the number of such pins.